Skip to main content


Don’t have an account yet? Register one!

Registration or login is required to send inquiries

Only registered users can send inquiries. Please register or login to continue.

P1 - D3.1 Report on Exa-enabling enhancements and benchmarks


Public material


The progress on the development of Exascale enabling technologies on the EXCELLERAT core codes is presented for the first year of the project. The developments have been guided by the definition of an individual code development roadmap in collaboration with Work Package 2 (WP2) and WP4, so the demonstration of Exascale simulations with the use cases can be achieved. From this roadmap, several requirements were identified (see D2.1 “Reference Applications: Roadmap and Challenges” [1]) and a summary of the activities conducted to address these requirements is presented here. Two fundamental activities are associated with these developments, Task 3.1 focused on node-level performance and Task 3.2 on system-level performance engineering. Note that the main changes in the evolution of HPC systems are occurring at the node level. This is a major reason to have a specific task focused on this topic.

In this first year, the activities carried out by the partners on these tasks have been focused on auditing the performance at the node level (DLR, BSC, KTH, CERFACS), enabling the utilization of accelerators through the directives-based language OpenACC (BSC, KTH), developing new data structures to better exploit new architectures (CERFACS, BSC) and developing techniques for the introduction of FPGAs on the CoE’s codes (UEDIN).

The second major activity is focused on identifying and overcoming bottlenecks at the system level that will arise on the road to Exascale. In this first year, the activities carried out by the partners have been focused on auditing the performance and system level and identifying bottlenecks (DLR, KTH, CERFACS), improving the strong scaling of the codes (CERFACS, KTH) and designing and implementing new distributed memory load balancing strategies (BSC). The activities on this WP also include the development of a benchmark suite for each code to be able to test and monitor the evolution of the codes, and the development of an efficient data transfer and dispatching strategy to operate the codes in an HPC cluster. Meshing activities have recently started and a compilation of information from the partners involved in these tasks (KTH, CERFACS and BSC) has been conducted.


Find the deliverable here. 


This deliverable was developed within the EXCELLERAT P1 Project phase. 


Public Project Deliverable