P1 - D3.2 Report on Exa-Enabling Enhancements and Benchmarks

Type

Public material

Description

The progress on the development of Exascale enabling technologies on the EXCELLERAT core codes is presented for the second year of the project. The developments have been driven by the definition of an individual code development roadmap in collaboration with WP2 and WP4 to demonstrate Exascale simulations for the use-cases.

From this roadmap, several requirements were identified (see D2.1, and D2.2 on” Reference_Applications_Roadmap and Challenges”) and a summary of the activities conducted to address these requirements is presented here. Two fundamental activities are associated with these developments: i) Task 3.1 focused on node-level performance and ii) Task 3.2 on system-level performance engineering. Note that main changes in the evolution of HPC systems are occurring at node level. This is a major reason to have a specific task focused on this topic.

In this second year, the activities carried out by the partners on these tasks have focused on the development of the application demonstrators of the use-cases. At node level (Task 3.1), the partners' developments have focused on porting the codes to GPUs and the new vectorial architecture SX-Aurora from NEC. The memory features of the modern AMD Epyc 2 have also been investigated. Finally, aspects related to intra-node parallelization, such as load balancing and OpenMP threading optimizations, have been considered. At the system level (Task 3.2), the focus has been on strong scaling analyses and on the optimization of the communication kernels. Regarding the advanced meshing techniques (Task 3.3), most of the work has been performed on the core code Alya, where the AMR workflow has been completed, and on the code AVBP, where an in-house implementation using the TREE PART domain decomposition library has been performed. For AVBP, different error estimators for AMR have been tested. Regarding emerging technologies, the focus has been placed on FPGAs and advanced developments for GPUs and ARM-based architectures.

The advances in HPC algorithms and computational methodologies presented here are part of the expertise of the EXCELLERAT consortium and conform services that EXCELLERAT is delivering to the engineering community.

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This deliverable was developed within the EXCELLERAT P1 Project phase.