Verificarlo: Floating-point Computing Verification, Debugging, and Optimization
10.03.2020 - 10.03.2020
Description
Description
Despite being the most widely used standard, IEEE 754 floating point numbers are a common source of non-reproducibility, inaccuracy, bugs, and performance issue in HPC simulations. Floating Point accuracy and performance are crucial for every new optimization in computer architectures or compilers, such as new vector instruction set, Fused Multiple-Add (FMA), or Bfloat16 support. Indeed, when such changes occurs, many industrial HPC codes reveal unknown bugs or are unable to take full advantage of the latest hardware accelerators. In that context, we propose the Verificarlo framework (https://github.com/verificarlo/verificarlo) that address floating point verification, debugging, and optimization, including mixed precision usage. It carries the three following objectives:
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Reproducibility: when an application or some pieces of code need to be reproducible up to a given threshold, it is tedious to track down numerical bugs to fix the situation when the reproducibility criterion is not met. By implementing advance debugging localization technique applied to numerical criterion, Verificarlo helps the users to debug and build reproducible application.
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Portability across HW and SW: when taking the best advantage of new hardware and software optimizations, the result of an application might be significantly different. Verificarlo provides a verification strategy by using Monte Carlo arithmetic. It is complementary to classical input parameter uncertainty quantification to measure the significance of the floating point error regarding the problem to solve.
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Performance optimization: By lowering the required representation format of some computation and variables, benefits come at many architectural levels: increasing the effective vector bandwidth, saving cache and memory bandwidth and capacity, and finally improving energy consumption. The result is an improved time to solution and cost. Verificarlo proposes the Vprec tool to explore mixed precision implementation.
Web-url
https://github.com/verificarlo/verificarlo
Streaming
Presenters
Eric Petit - Exascale Computing Research Lab (CEA-UVSQ-Intel) - Eric Petit joined Intel in 2017 as a senior research engineer in the Exascale Computing Research Lab (CEA-UVSQ-Intel). He received in 2009 his Ph.D. from University of Rennes at INRIA working on compiler technology for GPGPU. After 2 years at University of Perpignan working on computer arithmetic, he joined for 6 years as a senior researcher the University of Versailles Saint-Quentin where he leads a team participating in various EU project. Dr. Petit’s current research interests are on preparing HPC applications for future exascale systems. His focuses are on computer arithmetic and innovative runtime environment.Gabriel Staffelbach - CERFACS
URL
https://github.com/verificarlo/verificarlo
